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» Testing Digital Circuits with Constraints
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ICCAD
2007
IEEE
151views Hardware» more  ICCAD 2007»
14 years 14 days ago
A design flow dedicated to multi-mode architectures for DSP applications
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis t...
Cyrille Chavet, Caaliph Andriamisaina, Philippe Co...
GIS
2011
ACM
13 years 2 days ago
Embedding rivers in triangulated irregular networks with linear programming
Data conflation is a major issue in GIS: different geospatial data sets covering overlapping regions, possibly obtained from different sources and using different acquisition ...
Marc J. van Kreveld, Rodrigo I. Silveira
ICCAD
2003
IEEE
195views Hardware» more  ICCAD 2003»
14 years 1 months ago
Vectorless Analysis of Supply Noise Induced Delay Variation
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
Sanjay Pant, David Blaauw, Vladimir Zolotov, Savit...
TVLSI
2008
176views more  TVLSI 2008»
13 years 8 months ago
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
Venkataraman Mahalingam, N. Ranganathan, J. E. Har...
FPGA
2009
ACM
159views FPGA» more  FPGA 2009»
14 years 3 months ago
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
Raphael Rubin, André DeHon