1001 search results - page 32 / 201 » Testing Formal Dialectic |
CHARME
2003
Springer
13 years 11 months ago
2003
Springer
In formal verification, we verify that a system is correct with respect to a specification. Even when the system is proven to be correct, there is still a question of how complete ...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
EMNLP
2008
13 years 9 months ago
2008
We present a novel method for discovering and modeling the relationship between informal Chinese expressions (including colloquialisms and instant-messaging slang) and their forma...
MEMOCODE
2010
IEEE
13 years 5 months ago
2010
IEEE
This paper describes a formal executable semantics for the Verilog hardware description language. The goal of our formalization is to provide a concise and mathematically rigorous...
ICSE
2001
IEEE-ACM
14 years 5 days ago
2001
IEEE-ACM
The paper addresses the formal specification, design and implementation of the behavioral component of graphical user interfaces. The complex sequences of visual events and action...