— We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanot...
Functional debugging often dominates the time and cost of the ASIC system development, mainly due to the limited controllability and observability of the storage elements in desig...
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
This paper introduces the concept of hierarchical cellular automata (HCA). The theory of HCA is developed over the Galois extension field (2 ), where each cell of the CA can store ...
Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaud...
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...