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EVOW
1999
Springer

Test Pattern Generation Under Low Power Constraints

14 years 3 months ago
Test Pattern Generation Under Low Power Constraints
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunication systems, make power management during test a critical problem. A Genetic Algorithm computes a set of redundant test sequences, then a genetic optimization algorithm selects the optimal subset of sequences able to reduce the consumed power, without reducing the fault coverage. Experimental results gathered on benchmark circuits show that our approach decreases the peak power consumption by 20% on the average with respect to the original test sequence generated ignoring the power dissipation problem, without affecting the fault coverage.
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re
Added 04 Aug 2010
Updated 04 Aug 2010
Type Conference
Year 1999
Where EVOW
Authors Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
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