This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthy...
In the previous, companion, paper [13] to this paper we introduced our general model of refinement, discussed ideas around determinism and interfaces that the general definition r...
FPGAs have been used in many applications to achieve orders-of-magnitude improvement in absolute performance and energy efficiency relative to conventional microprocessors. Despit...
: Interacting with video content can be very time-consuming, and solutions are needed to support people in the process of browsing a video so that they can efficiently interact wit...
Ynze van Houten, Mark van Setten, Jan Gerrit Schuu...
Although conceived for web services, it is shown how BPEL (Business Process Execution Language) can be used to orchestrate a collection of grid services. This is achieved using th...