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DATE
2005
IEEE
107views Hardware» more  DATE 2005»
14 years 1 months ago
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prio...
Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chak...
ITC
2003
IEEE
118views Hardware» more  ITC 2003»
14 years 1 months ago
Method of reducing contactor effect when testing high-precision ADCs
— Being able to test the intrinsic performance of a device under test (DUT) has always been the main goal of a test engineer. Achieving this goal is becoming increasingly diffic...
Gwenolé Maugard, Carsten Wegener, Tom O'Dwy...
ITC
2003
IEEE
139views Hardware» more  ITC 2003»
14 years 1 months ago
A Hybrid Coding Strategy For Optimized Test Data Compression
Store-and-generate techniques encode a given test set and regenerate the original test set during the test with the help of a decoder. Previous research has shown that runlength c...
Armin Würtenberger, Christofer S. Tautermann,...
GPCE
2003
Springer
14 years 1 months ago
A Case for Test-Code Generation in Model-Driven Systems
A primary goal of generative programming and model-driven ent is to raise the level of abstraction at which designers and developers interact with the software systems they are bui...
Matthew J. Rutherford, Alexander L. Wolf
ITC
1993
IEEE
148views Hardware» more  ITC 1993»
14 years 5 days ago
DELTEST: Deterministic Test Generation for Gate-Delay Faults
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
Udo Mahlstedt