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» Testing implementations of transactional memory
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IOLTS
2002
IEEE
99views Hardware» more  IOLTS 2002»
14 years 3 months ago
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
This paper proposes a new solution for the diagnosis of faults into embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuit...
Davide Appello, Alessandra Fudoli, Vincenzo Tancor...
LCPC
2007
Springer
14 years 4 months ago
Pillar: A Parallel Implementation Language
Abstract. As parallelism in microprocessors becomes mainstream, new programming languages and environments are emerging to meet the challenges of parallel programming. To support r...
Todd Anderson, Neal Glew, Peng Guo, Brian T. Lewis...
SIGUCCS
2003
ACM
14 years 3 months ago
Implementation of fee-based printing in student computing sites
After years of providing no-cost printing in its computing sites, the University of Delaware (UD) decided to move to a fee-based printing scheme for its student computing sites. T...
Carol Jarom, Steven J. Timmins
HOST
2009
IEEE
14 years 5 months ago
Local Heating Attacks on Flash Memory Devices
This paper shows how lasers can be used to implement modification attacks on EEPROM and Flash memory devices. This was achieved with inexpensive laser-diode module mounted on a mic...
Sergei P. Skorobogatov
ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
14 years 3 months ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus