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CODES
2005
IEEE
15 years 11 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
CODES
2005
IEEE
15 years 11 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
15 years 11 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
HT
2005
ACM
15 years 11 months ago
Processing link structures and linkbases in the web's open world linking
Hyperlinks are an essential feature of the World Wide Web, highly responsible for its success. XLink improves on HTML’s linking capabilities in several ways. In particular, link...
François Bry, Michael Eckert
ATAL
2005
Springer
15 years 11 months ago
Designing multiparty interaction support in Elva, an embodied tour guide
Although social research into group interaction has flourished since the 20th century, the technology of embodied conversational agents for handling multiparty interaction is stil...
Jun Zheng, Xiang Yuan, Yam San Chee
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