217 search results - page 29 / 44 » The Block-Based Trace Cache |
MICRO
2008
IEEE
14 years 4 months ago
2008
IEEE
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
ICDCS
2007
IEEE
14 years 4 months ago
2007
IEEE
State-of-the-art networked storage servers are equipped with increasingly powerful computing capability and large DRAM memory as storage caches. However, their contribution to the...
JUCS
2000
13 years 10 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
ASE
2005
13 years 10 months ago
2005
Techniques for efficiently evaluating future time Linear Temporal Logic (abbreviated LTL) formulae on finite execution traces are presented. While the standard models of LTL are i...
RT
2004
Springer
14 years 3 months ago
2004
Springer
We introduce a tiled 3D MIP map representation of global illumination data. The representation is an adaptive, sparse octree with a “brick” at each octree node; each brick con...