39 search results - page 3 / 8 » The CDAG: A Data Structure for Automatic Parallelization for... |
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
ICPP
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract—The Sparse Matrix-Vector Multiplication kernel exhibits limited potential for taking advantage of modern shared memory architectures due to its large memory bandwidth re...
IEEECIT
2010
IEEE
13 years 6 months ago
2010
IEEE
Reduction is a common component of many applications, but can often be the limiting factor for parallelization. Previous reduction work has focused on detecting reduction idioms a...
CGF
2010
13 years 7 months ago
2010
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of powe...