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» The Case for Analog Circuit Verification
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EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
13 years 11 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
PPSN
2010
Springer
13 years 5 months ago
Using Co-solvability to Model and Exploit Synergetic Effects in Evolution
Abstract. We introduce, analyze, and experimentally examine co-solvability, an ability of a solution to solve a pair of fitness cases (tests). Based on this concept, we devise a co...
Krzysztof Krawiec, Pawel Lichocki
STOC
2010
ACM
168views Algorithms» more  STOC 2010»
14 years 4 months ago
Non-commutative circuits and the sum-of-squares problem
We initiate a direction for proving lower bounds on the size of non-commutative arithmetic circuits. This direction is based on a connection between lower bounds on the size of no...
Pavel Hrubes, Avi Wigderson and Amir Yehudayoff
ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
14 years 23 days ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov
DATE
2009
IEEE
115views Hardware» more  DATE 2009»
13 years 11 months ago
Customizing IP cores for system-on-chip designs using extensive external don't-cares
Traditional digital circuit synthesis flows start from an HDL behavioral definition and assume that circuit functions are almost completely defined, making don't-care conditio...
Kai-Hui Chang, Valeria Bertacco, Igor L. Markov