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    DAC
    2010
    ACM
    156views Computer Architecture» more  DAC 2010»
    Circuit modeling for practical many-core architecture design exploration
    14 years 12 days ago
    Circuit modeling for practical many-core architecture design exploration
    Download  www.ece.ucdavis.edu
    Current tools for computer architecture design lack standard support for multi- and many-core development. We propose using circuit models to describe the multiple processor archi...
    Dean Truong, Bevan M. Baas
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    GLOBECOM
    2007
    IEEE
    128views Communications» more  GLOBECOM 2007»
    Efficient Scheduling for Heterogeneous Services in OFDMA Downlink
    14 years 11 days ago
    Efficient Scheduling for Heterogeneous Services in OFDMA Downlink
    Download  www.stanford.edu
    We consider optimal allocation of resources to users in a downlink OFDMA system to support heterogeneous applications consisting of both deadline-sensitive (DS) and best-effort (BE...
    Rajiv Agarwal, Vinay R. Majjigi, Rath Vannithamby,...
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    ASAP
    2007
    IEEE
    118views Hardware» more  ASAP 2007»
    Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
    13 years 10 months ago
    Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
    Download  vada.skku.ac.kr
    This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
    Götz Kappen, S. el Bahri, O. Priebe, Tobias G...
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    WALTD
    2008
    168views Education» more  WALTD 2008»
    Accessible Interfaces for Educational Multimedia Contents
    13 years 10 months ago
    Accessible Interfaces for Educational Multimedia Contents
    Download  sunsite.informatik.rwth-aachen.de
    The use of technology is growing in every field of education, and not only in the education of disabled students but also as a learning resource for everybody. The teachers are mo...
    Lourdes Moreno, Ana Iglesias, Paloma Martín...
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    CSREAESA
    2003
    160views Embedded Systems» more  CSREAESA 2003»
    Worst Case Execution Time Analysis for Petri Net Models of Embedded Systems
    13 years 10 months ago
    Worst Case Execution Time Analysis for Petri Net Models of Embedded Systems
    Download  www.c-lab.de
    We present an approach for Worst-Case Execution Time (WCET) Analysis of embedded system software, that is generated from Petri net specifications. The presented approach is part ...
    Friedhelm Stappert, Carsten Rust
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