Abstract. An energy-efficient power-aware design is highly desirable for digital signal processing functions that encounter a wide diversity of operating scenarios in battery-power...
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
Microfluidics-based biochips offer exciting possibilities for highthroughput sequencing, parallel immunoassays, blood chemistry for clinical diagnostics, DNA sequencing, and envir...