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» The Complexity of Valued Constraint Models
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VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
14 years 8 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
CVPR
2009
IEEE
14 years 3 months ago
Learning multi-modal densities on Discriminative Temporal Interaction Manifold for group activity recognition
While video-based activity analysis and recognition has received much attention, existing body of work mostly deals with single object/person case. Coordinated multi-object activi...
Ruonan Li, Rama Chellappa, Shaohua Kevin Zhou
GLVLSI
2009
IEEE
122views VLSI» more  GLVLSI 2009»
14 years 3 months ago
Enhancing SAT-based sequential depth computation by pruning search space
The sequential depth determines the completeness of bounded model checking in design verification. Recently, a SATbased method is proposed to compute the sequential depth of a de...
Yung-Chih Chen, Chun-Yao Wang
ICASSP
2009
IEEE
14 years 3 months ago
RLS-weighted Lasso for adaptive estimation of sparse signals
The batch least-absolute shrinkage and selection operator (Lasso) has well-documented merits for estimating sparse signals of interest emerging in various applications, where obse...
Daniele Angelosante, Georgios B. Giannakis
IPPS
2009
IEEE
14 years 3 months ago
Enabling high-performance memory migration for multithreaded applications on LINUX
As the number of cores per machine increases, memory architectures are being redesigned to avoid bus contention and sustain higher throughput needs. The emergence of Non-Uniform M...
Brice Goglin, Nathalie Furmento