Sciweavers

68 search results - page 4 / 14
» The Concurrent Matching Switch Architecture
Sort
View
DATE
2007
IEEE
81views Hardware» more  DATE 2007»
14 years 1 months ago
Using the inter- and intra-switch regularity in NoC switch testing
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
Mohammad Hosseinabady, Atefe Dalirsani, Zainalabed...
SIGCOMM
2010
ACM
13 years 7 months ago
SwitchBlade: a platform for rapid deployment of network protocols on programmable hardware
We present SwitchBlade, a platform for rapidly deploying custom protocols on programmable hardware. SwitchBlade uses a pipeline-based design that allows individual hardware module...
Muhammad Bilal Anwer, Murtaza Motiwala, Muhammad M...
ISPAN
2005
IEEE
14 years 1 months ago
A Fast Noniterative Scheduler for Input-Queued Switches with Unbuffered Crossbars
Most high-end switches use an input-queued or a combined input- and output-queued architecture. The switch fabrics of these architectures commonly use an iterative scheduling syst...
Kevin F. Chen, Edwin Hsing-Mean Sha, S. Q. Zheng
ISLPED
1997
ACM
72views Hardware» more  ISLPED 1997»
13 years 11 months ago
A capacitor-based D/A converter with continuous time output for low-power applications
A digital to analog converter has been developed using switched capacitors as the basic DAC elements. The use of switching capacitors provides excellent matching without sacrifici...
Lapoe Lynn, Paul Ferguson Jr.
CONCURRENCY
2004
151views more  CONCURRENCY 2004»
13 years 7 months ago
User transparency: a fully sequential programming model for efficient data parallel image processing
Although many image processing applications are ideally suited for parallel implementation, most researchers in imaging do not benefit from high performance computing on a daily b...
Frank J. Seinstra, Dennis Koelma