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MEMOCODE
2006
IEEE
14 years 1 months ago
Latency-insensitive design and central repetitive scheduling
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...
Julien Boucaron, Robert de Simone, Jean-Vivien Mil...
STOC
2010
ACM
181views Algorithms» more  STOC 2010»
13 years 8 months ago
Load balancing and orientability thresholds for random hypergraphs
Let h > w > 0 be two fixed integers. Let H be a random hypergraph whose hyperedges are uniformly of size h. To w-orient a hyperedge, we assign exactly w of its vertices posi...
Pu Gao, Nicholas C. Wormald
CAL
2010
13 years 4 months ago
SMT-Directory: Efficient Load-Load Ordering for SMT
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any single thread appear to occur in program order to all other threads. Out-of-order execu...
A. Hilton, A. Roth
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
14 years 4 months ago
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design
– Many embedded system designs usually impose (hard) read-time constraints on tasks. Thus, computing a tight upper bound of the worst case execution time (WCET) of a software is ...
Junhyung Um, Taewhan Kim
ISCA
2010
IEEE
239views Hardware» more  ISCA 2010»
14 years 27 days ago
Sentry: light-weight auxiliary memory access control
Light-weight, flexible access control, which allows software to regulate reads and writes to any granularity of memory region, can help improve the reliability of today’s multi...
Arrvindh Shriraman, Sandhya Dwarkadas