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DAC
2008
ACM
14 years 10 months ago
Robust chip-level clock tree synthesis for SOC designs
A key problem that arises in System-on-a-Chip (SOC) designs of today is the Chip-level Clock Tree Synthesis (CCTS). CCTS is done by merging all the clock trees belonging to differ...
Anand Rajaram, David Z. Pan
RECOMB
2005
Springer
14 years 9 months ago
A Framework for Orthology Assignment from Gene Rearrangement Data
Abstract. Gene rearrangements have been used successfully in phylogenetic reconstruction and comparative genomics, but usually under the assumption that all genomes have the same g...
Krister M. Swenson, Nicholas D. Pattengale, Bernar...
BPM
2009
Springer
119views Business» more  BPM 2009»
14 years 3 months ago
A Formal Model for Process Context Learning
Process models are considered to be a major asset in modern business organizations. They are expected to apply to all the possible business contexts in which the process may be exe...
Johny Ghattas, Pnina Soffer, Mor Peleg
ISCA
1998
IEEE
102views Hardware» more  ISCA 1998»
14 years 1 months ago
Dynamic History-length Fitting: A Third Level of Adaptivity for Branch Prediction
Accurate branch prediction is essential for obtaining high performance in pipelined superscalar processors that execute instructions speculatively. Some of the best current predic...
Toni Juan, Sanji Sanjeevan, Juan J. Navarro
AMAST
1998
Springer
14 years 1 months ago
Scheduling Algebra
The goal of this paper is to develop an algebraic theory of process scheduling. We specify a syntax for denoting processes composed of actions with given durations. Subsequently, w...
Rob J. van Glabbeek, Peter Rittgen