In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid...
An important part of a distributed system design is the workload sharing among the processors. This includes partitioningthe arriving jobs into tasks that can be executed in paral...
Layering of protocols o ers several well-known advantages, but typically leads to performance ine ciencies. We present a model for layering, and point out where the performance pr...
CAD tool interoperability issues are a recurring impediment to constructing a design methodology, especially if the methodology incorporates point tools from several vendors. Failu...
Mike Murray, Uwe B. Meding, Bill Berg, Yatin Trive...
-- This paper presents an efficient method for the timing verification of concurrent systems, modeled as labeled Timed Petri nets. The verification problems we consider require us ...