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» The Design and Performance of a Conflict-Avoiding Cache
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HPCA
2009
IEEE
16 years 6 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
ICPP
2005
IEEE
15 years 11 months ago
Exploring Processor Design Options for Java-Based Middleware
Java-based middleware is a rapidly growing workload for high-end server processors, particularly Chip Multiprocessors (CMP). To help architects design future microprocessors to ru...
Martin Karlsson, Erik Hagersten, Kevin E. Moore, D...
150
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DATE
2008
IEEE
115views Hardware» more  DATE 2008»
16 years 16 days ago
Synthesizing Synchronous Elastic Flow Networks
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...
Greg Hoover, Forrest Brewer
CIKM
2007
Springer
16 years 7 days ago
Optimal proactive caching in peer-to-peer network: analysis and application
As a promising new technology with the unique properties like high efficiency, scalability and fault tolerance, Peer-toPeer (P2P) technology is used as the underlying network to b...
Weixiong Rao, Lei Chen 0002, Ada Wai-Chee Fu, Ying...
IEEEPACT
2005
IEEE
15 years 11 months ago
Maximizing CMP Throughput with Mediocre Cores
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
John D. Davis, James Laudon, Kunle Olukotun