Sciweavers

867 search results - page 112 / 174
» The Design and Performance of a Conflict-Avoiding Cache
Sort
View
SIGCOMM
2004
ACM
15 years 11 months ago
The design and implementation of a next generation name service for the internet
Name services are critical for mapping logical resource names to physical resources in large-scale distributed systems. The Domain Name System (DNS) used on the Internet, however,...
Venugopalan Ramasubramanian, Emin Gün Sirer
ISCA
2011
IEEE
238views Hardware» more  ISCA 2011»
14 years 9 months ago
Rebound: scalable checkpointing for coherent shared memory
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
Rishi Agarwal, Pranav Garg, Josep Torrellas
CODES
2011
IEEE
14 years 5 months ago
SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs
Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardware complexity. In this paper we present SoC-TM, an integrated HW/SW solution for tr...
Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R....
179
Voted
CF
2005
ACM
15 years 8 months ago
A case for a working-set-based memory hierarchy
Modern microprocessor designs continue to obtain impressive performance gains through increasing clock rates and advances in the parallelism obtained via micro-architecture design...
Steve Carr, Soner Önder
ISCA
1995
IEEE
98views Hardware» more  ISCA 1995»
15 years 9 months ago
Instruction Fetching: Coping with Code Bloat
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...
Richard Uhlig, David Nagle, Trevor N. Mudge, Stuar...