867 search results - page 115 / 174 » The Design and Performance of a Conflict-Avoiding Cache |
185
click to vote
MICRO
2007
IEEE
16 years 7 days ago
2007
IEEE
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
162
click to vote
CASES
2007
ACM
15 years 10 months ago
2007
ACM
In this paper we describe the design and implementation of a flexible, and extensible, just-in-time ARM simulator designed to run co-operatively with a multi-core DSP simulator on...
174
click to vote
RSP
2000
IEEE
15 years 10 months ago
2000
IEEE
Reconfigurable instruction set processors have the capability to adapt their instruction sets to the application being executed through a reconfiguration in their hardware. Throug...
188
click to vote
PDPTA
1996
15 years 7 months ago
1996
Dynamic data distributions offer a number of performance benefits, but require more sophisticated compiler support and incur run-time overhead. We investigate attainable benefits ...
173
click to vote
ISCA
1995
IEEE
15 years 9 months ago
1995
IEEE
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...