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» The Design and Performance of a Conflict-Avoiding Cache
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HPCA
2007
IEEE
16 years 6 months ago
A Scalable, Non-blocking Approach to Transactional Memory
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
Hassan Chafi, Jared Casper, Brian D. Carlstrom, Au...
RTAS
2010
IEEE
15 years 4 months ago
DARTS: Techniques and Tools for Predictably Fast Memory Using Integrated Data Allocation and Real-Time Task Scheduling
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
Sangyeol Kang, Alexander G. Dean
ICS
2010
Tsinghua U.
15 years 7 months ago
Timing local streams: improving timeliness in data prefetching
Data prefetching technique is widely used to bridge the growing performance gap between processor and memory. Numerous prefetching techniques have been proposed to exploit data pa...
Huaiyu Zhu, Yong Chen, Xian-He Sun
MSS
2007
IEEE
86views Hardware» more  MSS 2007»
16 years 5 days ago
RAIF: Redundant Array of Independent Filesystems
Storage virtualization and data management are well known problems for individual users as well as large organizations. Existing storage-virtualization systems either do not suppo...
Nikolai Joukov, Arun M. Krishnakumar, Chaitanya Pa...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
15 years 3 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt