867 search results - page 142 / 174 » The Design and Performance of a Conflict-Avoiding Cache |
171
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ISCA
2005
IEEE
15 years 11 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
179
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MOBISYS
2007
ACM
16 years 5 months ago
2007
ACM
In this work, we investigate the use of directional antennas and beam steering techniques to improve performance of 802.11 links in the context of communication between a moving v...
178
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CF
2006
ACM
15 years 11 months ago
2006
ACM
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
152
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ICPP
2009
IEEE
16 years 14 days ago
2009
IEEE
— High-end computing (HEC) systems have passed the petaflop barrier and continue to move toward the next frontier of exascale computing. As companies and research institutes con...
195
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VLDB
1999
ACM
15 years 10 months ago
1999
ACM
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...