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» The Design and Performance of a Conflict-Avoiding Cache
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ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
16 years 2 months ago
Implementation and Evaluation of On-Chip Network Architectures
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...
NOSSDAV
2009
Springer
16 years 9 days ago
Power efficient real-time disk scheduling
Hard-disk drive power consumption reduction methods focus mainly on increasing the amount of time the disk is in standby mode (disk spun down) by implementing aggressive data read...
Damien Le Moal, Donald Molaro, Jorge Campello
INFOCOM
2007
IEEE
16 years 2 days ago
A Proxy View of Quality of Domain Name Service
— The Domain Name System (DNS) provides a critical service for the Internet – mapping of user-friendly domain names to their respective IP addresses. Yet, there is no standard ...
Lihua Yuan, Krishna Kant, Prasant Mohapatra, Chen-...
MICRO
2002
IEEE
122views Hardware» more  MICRO 2002»
15 years 10 months ago
Microarchitectural denial of service: insuring microarchitectural fairness
Simultaneous multithreading seeks to improve the aggregate computation bandwidth of a processor core by sharing resources such as functional units, caches, TLB and so on. To date,...
Dirk Grunwald, Soraya Ghiasi
CODES
2000
IEEE
15 years 10 months ago
Co-design of interleaved memory systems
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
Hua Lin, Wayne Wolf