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» The Design and Performance of a Conflict-Avoiding Cache
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IMS
2000
125views Hardware» more  IMS 2000»
14 years 2 days ago
Compiler-Directed Cache Line Size Adaptivity
The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size tha...
Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbau...
CASES
2010
ACM
13 years 6 months ago
Improved procedure placement for set associative caches
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
Yun Liang, Tulika Mitra
ICS
2009
Tsinghua U.
14 years 3 months ago
Zero-content augmented caches
It has been observed that some applications manipulate large amounts of null data. Moreover these zero data often exhibit high spatial locality. On some applications more than 20%...
Julien Dusser, Thomas Piquet, André Seznec
CSREAESA
2003
13 years 10 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...
ISLPED
2006
ACM
117views Hardware» more  ISLPED 2006»
14 years 2 months ago
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)
As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essent...
Samuel Rodríguez, Bruce L. Jacob