Compiler-Directed Cache Line Size Adaptivity

The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size that is xed at design time. Miss rates for di erent applications can be improved if the line size could be adjusted dynamically at run time. We propose a system where the compiler can set the cache line size for di erent portions of the program and we show that the miss rate is greatly reduced as a result of this dynamic resizing.

• Type: Conference
• Year: 2000
• Where: IMS
• Authors: Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta
• Keywords: Cache Memory, Cache Memory System, Hardware, IMS 2000, Line Size