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» The Design of High-Performance Microprocessors at Digital
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HPCA
2008
IEEE
14 years 8 months ago
DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors
Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. Noise-...
Meeta Sharma Gupta, Krishna K. Rangan, Michael D. ...
HPCA
2009
IEEE
14 years 2 months ago
Soft error vulnerability aware process variation mitigation
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
Xin Fu, Tao Li, José A. B. Fortes
ISLPED
2003
ACM
152views Hardware» more  ISLPED 2003»
14 years 28 days ago
An MTCMOS design methodology and its application to mobile computing
The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are use...
Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae P...
ICSE
2008
IEEE-ACM
14 years 8 months ago
Design and implementation of the software architecture for a 3-D reconstruction system in medical imaging
The design and implementation of the reconstruction system in medical X-ray imaging is a challenging issue due to its immense computational demands. In order to ensure an efficien...
Holger Scherl, Stefan Hoppe, Markus Kowarschik, Jo...
ASPLOS
2009
ACM
14 years 8 months ago
Mixed-mode multicore reliability
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...