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ASPDAC
2008
ACM
94views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
Sujan Pandey, Rolf Drechsler
DFT
2000
IEEE
106views VLSI» more  DFT 2000»
13 years 11 months ago
Self-Configuration of a Large Area Integrated Multiprocessor System for Video Applications
We present a configuration technique for a Large Area Integrated Circuit (LAIC) which is manufactured by wafer stepping. A LAIC consists of four identical subsystems, i.e., a subs...
Markus Rudack, Michael Redeker, Dieter Treytnar, O...
ACSAC
2000
IEEE
13 years 11 months ago
Virtual Enterprise Networks: The Next Generation of Secure Enterprise Networking
We present a vision of computing environments in which enterprise networks are built using untrusted public infrastructures. The vision allows for networks to dynamically change d...
Germano Caronni, S. Kumar, Christoph L. Schuba, Gl...
WWW
2003
ACM
14 years 18 days ago
AnswerBus News Engine
AnswerBus News Engine1 is a question answering system using the contents of CNN Web site2 as its knowledge base. Comparing to other question answering systems including its previo...
Zhiping Zheng
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
14 years 29 days ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...