100 search results - page 9 / 20 » The Effect of Instruction Set Complexity on Program Size and... |
HPCA
2002
IEEE
13 years 11 months ago
2002
IEEE
Configurations of contemporary DRAM memory systems become increasingly complex. A recent study [5] shows that application performance is highly sensitive to choices of configura...
LCPC
2000
Springer
13 years 10 months ago
2000
Springer
Embedded systems consisting of the application program ROM, RAM, the embedded processor core, and any custom hardware on a single wafer are becoming increasingly common in applicat...
MICRO
1997
IEEE
13 years 11 months ago
1997
IEEE
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
DAC
2004
ACM
14 years 7 months ago
2004
ACM
Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio...