237 search results - page 13 / 48 » The Energy Efficiency of IRAM Architectures |
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
GLOBECOM
2006
IEEE
14 years 1 months ago
2006
IEEE
— Reducing energy consumption has been a recent focus of wireless sensor network research. Topology control explores the potential that a dense network has for energy savings. On...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges in...
ICCD
2003
IEEE
14 years 4 months ago
2003
IEEE
This paper investigates some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in pe...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...