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» The Energy Efficiency of IRAM Architectures
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DAC
2005
ACM
14 years 8 months ago
Energy optimal speed control of devices with discrete speed sets
We obtain analytically, the energy optimal speed profile of a generic multi-speed device with a discrete set of speeds, to execute a given task within a given time. Current implem...
Ravishankar Rao, Sarma B. K. Vrudhula
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
14 years 28 days ago
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the domi...
Alberto Macii, Enrico Macii, Fabrizio Crudo, Rober...
CF
2004
ACM
14 years 1 months ago
The happy marriage of architecture and application in next-generation reconfigurable systems
New applications and standards are first conceived only for functional correctness and without concerns for the target architecture. The next challenge is to map them onto an arch...
Ingrid Verbauwhede, Patrick Schaumont
ANCS
2008
ACM
13 years 9 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
FPL
2010
Springer
111views Hardware» more  FPL 2010»
13 years 5 months ago
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays
Abstract--Efficient storage in spatial processors is increasingly important as such devices get larger and support more concurrent operations. Unlike sequential processors that rel...
Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebe...