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» The Energy Efficiency of IRAM Architectures
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MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 7 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
ASPLOS
2012
ACM
12 years 3 months ago
Reflex: using low-power processors in smartphones without knowing them
To accomplish frequent, simple tasks with high efficiency, it is necessary to leverage low-power, microcontroller-like processors that are increasingly available on mobile systems...
Felix Xiaozhu Lin, Zhen Wang, Robert LiKamWa, Lin ...
CAINE
2006
13 years 9 months ago
A multiobjective evolutionary approach for constrained joint source code optimization
The synergy of software and hardware leads to efficient application expression profile (AEP) not only in terms of execution time and energy but also optimal architecture usage. We...
Naeem Zafar Azeemi
NOSSDAV
2005
Springer
14 years 1 months ago
Power-efficient streaming for mobile terminals
Wireless Network Interface (WNI) is one of the most critical components for power efficiency in multimedia streaming to mobile devices. A common strategy to save power is to switc...
Jari Korhonen, Ye Wang
DAC
2006
ACM
13 years 9 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...