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» The Fail-Heterogeneous Architectural Model
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120
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DAC
1994
ACM
15 years 7 months ago
RC Interconnect Optimization Under the Elmore Delay Model
An e cient solution to the wire sizing problem WSP usingthe Elmoredelaymodelisproposed. Two formulations of the problem are put forth: in the rst, the minimum interconnect delay i...
Sachin S. Sapatnekar
120
Voted
APCSAC
2001
IEEE
15 years 7 months ago
Retargetable Cache Simulation Using High Level Processor Models
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simula...
Rajiv A. Ravindran, Rajat Moona
108
Voted
FLAIRS
2008
15 years 5 months ago
ThomCat: A Bayesian Blackboard Model of Hierarchical Temporal Perception
We present a Bayesian blackboard system for temporal perception, applied to a minidomain task in musical scene analysis. It is similar to the classic Copycat architecture (Hofstad...
Charles W. Fox
146
Voted
ICCBSS
2005
Springer
15 years 9 months ago
Resolving Architectural Mismatches of COTS Through Architectural Reconciliation
Abstract. The integration of COTS components into a system under development entails architectural mismatches. These have been tackled, so far, at the component level, through comp...
Paris Avgeriou, Nicolas Guelfi
101
Voted
EUROPAR
2006
Springer
15 years 7 months ago
A Multi-level Scheduler for the Grid Computing YML Framework
This paper presents the integration of a multi-level scheduler in the YML architecture. It demonstrates the advantages of this architecture based on a component model and why it is...
Sébastien Noël, Olivier Delannoy, Nahi...