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ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
13 years 11 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
IJCNN
2008
IEEE
14 years 1 months ago
Efficient and low-complexity image coding with the lifting scheme and modified SPIHT
—In this paper, we propose an efficient and low complexity image coding algorithm based on the lifting wavelet transform and listless modified SPIHT (LWT-LMSPIHT). LWT-LMSPIHT jo...
Hong Pan, Wan-Chi Siu, Ngai-Fong Law
FPL
2010
Springer
111views Hardware» more  FPL 2010»
13 years 5 months ago
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays
Abstract--Efficient storage in spatial processors is increasingly important as such devices get larger and support more concurrent operations. Unlike sequential processors that rel...
Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebe...
HPCA
2011
IEEE
12 years 11 months ago
A new server I/O architecture for high speed networks
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
Guangdeng Liao, Xia Znu, Laxmi N. Bhuyan
ANCS
2006
ACM
13 years 11 months ago
Packet classification using coarse-grained tuple spaces
While the problem of high performance packet classification has received a great deal of attention in recent years, the research community has yet to develop algorithmic methods t...
Haoyu Song, Jonathan S. Turner, Sarang Dharmapurik...