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» The Garp Architecture and C Compiler
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ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
13 years 11 months ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson
WSC
1998
13 years 11 months ago
MODSIM III - a Tutorial with Advances in Database Access and HLA Support
MODSIM II is an object-oriented discrete event simulation language featuring extensive run-time libraries, graphical user interface and results presentation tools, database access...
John Goble, Brian Wood
DAC
2007
ACM
14 years 10 months ago
Program Mapping onto Network Processors by Recursive Bipartitioning and Refining
Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network a...
Jia Yu, Jingnan Yao, Jun Yang 0002, Laxmi N. Bhuya...
EMSOFT
2004
Springer
14 years 3 months ago
Towards direct execution of esterel programs on reactive processors
Esterel is a system-level language for the modelling, verification and synthesis of control dominated (reactive) embedded systems. Existing Esterel compilers generate intermediat...
Partha S. Roop, Zoran A. Salcic, M. W. Sajeewa Day...
IWMM
2010
Springer
137views Hardware» more  IWMM 2010»
14 years 1 months ago
The locality of concurrent write barriers
Concurrent and incremental collectors require barriers to ensure correct synchronisation between mutator and collector. The overheads imposed by particular barriers on particular ...
Laurence Hellyer, Richard Jones, Antony L. Hosking