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» The Geometry of Strict Maximality
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FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
14 years 1 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
SIGMETRICS
2010
ACM
150views Hardware» more  SIGMETRICS 2010»
14 years 1 months ago
Incentive compatibility and dynamics of congestion control
This paper studies under what conditions congestion control schemes can be both efficient, so that capacity is not wasted, and incentive compatible, so that each participant can m...
Brighten Godfrey, Michael Schapira, Aviv Zohar, Sc...
ICRA
2000
IEEE
96views Robotics» more  ICRA 2000»
14 years 1 months ago
Design of Synchronized Supply Chains: A Six Sigma Tolerancing Approach
A supply chain network can be viewed as a network of facilities in which a customer order will flow through internal business processes such as procurement, production, and transp...
Y. Narahari, Nukala Viswanadham, R. Bhattacharya
CONCUR
1998
Springer
14 years 26 days ago
On Discretization of Delays in Timed Automata and Digital Circuits
In this paper we solve the following problem: \given a digital circuit composed of gates whose real-valued delays are in an integerbounded interval, is there a way to discretize ti...
Eugene Asarin, Oded Maler, Amir Pnueli
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
14 years 26 days ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar