This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
This paper studies under what conditions congestion control schemes can be both efficient, so that capacity is not wasted, and incentive compatible, so that each participant can m...
Brighten Godfrey, Michael Schapira, Aviv Zohar, Sc...
A supply chain network can be viewed as a network of facilities in which a customer order will flow through internal business processes such as procurement, production, and transp...
In this paper we solve the following problem: \given a digital circuit composed of gates whose real-valued delays are in an integerbounded interval, is there a way to discretize ti...
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...