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DAC
1998
ACM
14 years 1 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha
ICS
1998
Tsinghua U.
14 years 1 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
DAC
1997
ACM
14 years 1 months ago
Electronic Component Information Exchange (ECIX)
A number of industry trends are shaping the requirements for IC and electronic equipment design. The density and complexity of circuit technologies have increased to a point where...
Donald R. Cottrell
ASPLOS
1996
ACM
14 years 1 months ago
An Integrated Compile-Time/Run-Time Software Distributed Shared Memory System
On a distributed memory machine, hand-coded message passing leads to the most efficient execution, but it is difficult to use. Parallelizing compilers can approach the performance...
Sandhya Dwarkadas, Alan L. Cox, Willy Zwaenepoel
PLDI
1990
ACM
14 years 1 months ago
A Fresh Look at Optimizing Array Bound Checking
- This paper describes techniques for optimizing range checks performed to detect array bound violations. In addition to the elimination of range check:s, the optimizations discuss...
Rajiv Gupta