2424 search results - page 114 / 485 » The High Level Architecture for Simulations |
DSD
2007
IEEE
14 years 3 months ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
INFOCOM
2010
IEEE
13 years 7 months ago
2010
IEEE
— Internet traffic is expected to grow phenomenally over the next five to ten years, and to cope with such large traffic volumes, core networks are expected to scale to capaci...
SPIESR
1996
13 years 10 months ago
1996
Multimedia interfaces increase the need for large image databases, capable of storing and reading streams of data with strict synchronicity and isochronicity requirements. In orde...
DSD
2004
IEEE
14 years 19 days ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
ICRA
2002
IEEE
14 years 1 months ago
2002
IEEE
In the present paper a system for generation of topological maps is going to be presented. This system is considered as one of the deliberative skills of the mobile robots architec...