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» The High Level Architecture for Simulations
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SIGARCH
2008
96views more  SIGARCH 2008»
13 years 8 months ago
Towards hybrid last level caches for chip-multiprocessors
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...
Li Zhao, Ravi Iyer, Mike Upton, Don Newell
ACMSE
2006
ACM
14 years 2 months ago
HELLAS: a specialized architecture for interactive deformable object modeling
Applications involving interactive modeling of deformable objects require highly iterative, floating-point intensive numerical simulations. As the complexity of these models incr...
Shrirang M. Yardi, Benjamin Bishop, Thomas P. Kell...
EVOW
2008
Springer
13 years 10 months ago
Architecture Performance Prediction Using Evolutionary Artificial Neural Networks
The design of computer architectures requires the setting of multiple parameters on which the final performance depends. The number of possible combinations make an extremely huge ...
Pedro A. Castillo, Antonio Miguel Mora, Juan Juli&...
ICCAD
1993
IEEE
104views Hardware» more  ICCAD 1993»
14 years 1 months ago
Parallel timing simulation on a distributed memory multiprocessor
Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
Chih-Po Wen, Katherine A. Yelick
ICCD
2005
IEEE
176views Hardware» more  ICCD 2005»
14 years 5 months ago
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
Recent advances in Dynamic Power Management (DPM) techniques have resulted in designs that support a rich set of power management options, both at the hardware and software levels...
Shrirang M. Yardi, Karthik Channakeshava, Michael ...