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» The High Level Architecture for Simulations
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JPDC
2002
63views more  JPDC 2002»
13 years 8 months ago
Compiler-Optimized Simulation of Large-Scale Applications on High Performance Architectures
Vikram S. Adve, Rajive Bagrodia, Ewa Deelman, Rizo...
JPDC
2002
38views more  JPDC 2002»
13 years 8 months ago
Simulating Spatially Explicit Problems on High Performance Architectures
Ewa Deelman, Boleslaw K. Szymanski
FLAIRS
1998
13 years 10 months ago
Learning to Race: Experiments with a Simulated Race Car
Our focus is on designing adaptable agents for highly dynamic environments. Wehave implementeda reinforcement learning architecture as the reactive componentof a twolayer control ...
Larry D. Pyeatt, Adele E. Howe
CDES
2009
170views Hardware» more  CDES 2009»
13 years 9 months ago
Benchmarking GPU Devices with N-Body Simulations
Recent developments in processing devices such as graphical processing units and multi-core systems offer opportunities to make use of parallel techniques at the chip level to obt...
Daniel P. Playne, Mitchell Johnson, Kenneth A. Haw...
3DIC
2009
IEEE
169views Hardware» more  3DIC 2009»
14 years 1 months ago
3-D memory organization and performance analysis for multi-processor network-on-chip architecture
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid s...
Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerase...