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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
16 years 16 days ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
ICNP
2006
IEEE
16 years 5 days ago
RAIN: A Reliable Wireless Network Architecture
Abstract— Despite years of research and development, pioneering deployments of multihop wireless networks have not proven successful. The performance of routing and transport is ...
Chaegwon Lim, Haiyun Luo, Chong-Ho Choi
176
Voted
FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
15 years 10 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
176
Voted
ASPDAC
2005
ACM
102views Hardware» more  ASPDAC 2005»
15 years 8 months ago
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
Oliver Schliebusch, Anupam Chattopadhyay, David Ka...
MICCAI
2002
Springer
16 years 7 months ago
Macroscopic Modeling of Vascular Systems
Abstract. Angiogenesis, the growth of vascular structures, is an extremely complex biological process which has long puzzled scientists. Better physiological understanding of this ...
Dominik Szczerba, Gábor Székely