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» The High Level Architecture for Simulations
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DATE
2008
IEEE
112views Hardware» more  DATE 2008»
16 years 9 days ago
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
Paolo Bernardi, Matteo Sonza Reorda
LCTRTS
2007
Springer
15 years 12 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
MTA
2000
128views more  MTA 2000»
15 years 5 months ago
A CORBA Based QOS Support for Distributed Multimedia Applications
AdvanceobjectorientedcomputingplatformsuchastheCommonObjectRequestBrokerArchitecture (CORBA) provides a conducive and standardized framework for the development of distributed appl...
Hung Keng Pung, Wynne Hsu, Bhawani S. Sapkota, Law...
ISCA
2011
IEEE
269views Hardware» more  ISCA 2011»
14 years 9 months ago
Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
High assurance systems used in avionics, medical implants, and cryptographic devices often rely on a small trusted base of hardware and software to manage the rest of the system. ...
Mohit Tiwari, Jason Oberg, Xun Li 0001, Jonathan V...
DAC
2000
ACM
16 years 6 months ago
Unifying behavioral synthesis and physical design
eously demand shorter and less costly design cycles. Designing at higher levels of abstraction makes both objectives achievable, but enabling techniques like behavioral synthesis h...
William E. Dougherty, Donald E. Thomas