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ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
14 years 3 months ago
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...
SIGSOFT
1998
ACM
14 years 28 days ago
Formal Modeling and Analysis of the HLA Component Integration Standard
An increasingly important trend in the engineering of complex systems is the design of component integration standards. Such standards de ne rules of interaction and shared commun...
Robert Allen, David Garlan
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
14 years 2 months ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton
ISCAS
2005
IEEE
155views Hardware» more  ISCAS 2005»
14 years 2 months ago
Hyperblock formation: a power/energy perspective for high performance VLIW architectures
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
INFOCOM
2000
IEEE
14 years 1 months ago
Fast and Scalable Priority Queue Architecture for High-Speed Network Switches
-In this paper, we present a fast and scalable pipelined priority queue architecture for use in high-performance switches with support for fine-grained quality of service (QoS) gu...
Ranjita Bhagwan, Bill Lin