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» The High Level Architecture for Simulations
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CODES
2004
IEEE
14 years 15 days ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
JPDC
2007
86views more  JPDC 2007»
13 years 8 months ago
Strategies to create platforms for differentiated services from dedicated and opportunistic resources
This paper is proposing a new platform for implementing services in future service oriented architectures. The basic premise of our proposal is that by combining large volume of u...
Shah Asaduzzaman, Muthucumaru Maheswaran
SC
2005
ACM
14 years 2 months ago
Transparent, Incremental Checkpointing at Kernel Level: a Foundation for Fault Tolerance for Parallel Computers
We describe the software architecture, technical features, and performance of TICK (Transparent Incremental Checkpointer at Kernel level), a system-level checkpointer implemented ...
Roberto Gioiosa, José Carlos Sancho, Song J...
DAC
2004
ACM
14 years 9 months ago
System design for DSP applications in transaction level modeling paradigm
In this paper, we systematically define three transaction level TLMs), which reside at different levels of abstraction between the functional and the implementation model of a DSP...
Abhijit K. Deb, Axel Jantsch, Johnny Öberg
WSC
2001
13 years 10 months ago
Simulation application service providing (SIM-ASP)
This paper considers advantages and actual problems of web based simulation systems. Based on a review of environments and languages for web based simulation, some fundamental req...
Thomas Wiedemann