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» The High Level Architecture for Simulations
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ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
14 years 1 months ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá
ICCD
2007
IEEE
132views Hardware» more  ICCD 2007»
14 years 5 months ago
Post-layout comparison of high performance 64b static adders in energy-delay space
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
Sheng Sun, Carl Sechen
SAMOS
2007
Springer
14 years 2 months ago
Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration
The Sesame modeling and simulation framework aims at early and thus efficient system-level design space exploration of embedded multimedia system architectures. So far, Sesame onl...
Mark Thompson, Andy D. Pimentel
ASYNC
2006
IEEE
122views Hardware» more  ASYNC 2006»
14 years 2 months ago
A Level-Crossing Flash Asynchronous Analog-to-Digital Converter
Distributed sensor networks, human body implants, and hand-held electronics have tight energy budgets that necessitate low power circuits. Most of these devices include an analog-...
Filipp Akopyan, Rajit Manohar, Alyssa B. Apsel
CODES
2006
IEEE
14 years 2 months ago
Automatic generation of transaction level models for rapid design space exploration
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate suc...
Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rain...