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» The High Level Architecture for Simulations
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IMECS
2007
13 years 10 months ago
A Novel High Speed Chinese Abacus Multiplier
—In this paper, a novel Chinese abacus multiplier is presented. The architecture of a 4-bit multiplier is demonstrated. The simulation results of our work are compared with the 4...
Yi-Chieh Lin, Chien-Hung Lin, Zi-Yi Zhao, Yu-Zhi X...
DAC
2007
ACM
14 years 9 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...
SIGADA
2001
Springer
14 years 1 months ago
Targeting Ada95/DSA for distributed simulation of multiprotocol communication networks
The last years have seen an increasing, albeit restricted simulation of large-scale networks on shared memory parallel platforms. As the complexity of communication protocols and ...
Dhavy Gantsou
SIGCSE
2006
ACM
134views Education» more  SIGCSE 2006»
14 years 2 months ago
jFAST: a java finite automata simulator
Visualization and interactivity are valuable active learning techniques that can improve mastery of difficult concepts. In this paper we describe jFAST, an easy-to-use graphical s...
Timothy M. White, Thomas P. Way
CODES
2009
IEEE
14 years 3 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...