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DAC
1998
ACM
14 years 9 months ago
A Programming Environment for the Design of Complex High Speed ASICs
A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiver is used as a driver example. Compact descrip...
Patrick Schaumont, Serge Vernalde, Luc Rijnders, M...
ISM
2005
IEEE
83views Multimedia» more  ISM 2005»
14 years 2 months ago
Efficient and Fair Multi-Level Packet Scheduling for Differentiated Services
As the demands on quality of service (QoS) of real-time applications over the Internet increase, many research efforts have developed various packet scheduling schemes to support ...
Chin-Chi Wu, Hsien-Ming Wu, Woei Lin
TPDS
2010
125views more  TPDS 2010»
13 years 3 months ago
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level
The importance of transient faults is predicted to grow due to current technology trends of increased scale of integration. One of the components that will be significantly affecte...
Ricardo Fernández Pascual, José M. G...
ICCAD
2008
IEEE
103views Hardware» more  ICCAD 2008»
14 years 5 months ago
Hardware protection and authentication through netlist level obfuscation
—Hardware Intellectual Property (IP) cores have emerged as an integral part of modern System–on–Chip (SoC) designs. However, IP vendors are facing major challenges to protect...
Rajat Subhra Chakraborty, Swarup Bhunia
AINA
2009
IEEE
14 years 3 months ago
Modeling Web Request and Session Level Arrivals
This paper is focused on modeling Web request and session level arrival processes. We propose a statistically rigorous approach which includes testing for non-stationarity and Gau...
Xuan Wang, Katerina Goseva-Popstojanova