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» The ISPD98 circuit benchmark suite
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ICCAD
1995
IEEE
110views Hardware» more  ICCAD 1995»
14 years 1 months ago
Fast functional simulation using branching programs
This paper addresses the problem of speeding up functional (delayindependent)logic simulation for synchronousdigital systems. The problem needs very little new motivation – cycl...
Pranav Ashar, Sharad Malik
ISPD
2012
ACM
289views Hardware» more  ISPD 2012»
12 years 5 months ago
Keep it straight: teaching placement how to better handle designs with datapaths
As technology scales and frequency increases, a new design style is emerging, referred to as hybrid designs, which contain a mixture of random logic and datapath standard cell com...
Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanat...
ATS
2009
IEEE
111views Hardware» more  ATS 2009»
14 years 4 months ago
Dynamic Compaction in SAT-Based ATPG
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...
Alejandro Czutro, Ilia Polian, Piet Engelke, Sudha...
ASPDAC
2009
ACM
142views Hardware» more  ASPDAC 2009»
14 years 4 months ago
On the futility of statistical power optimization
In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this...
Jason Cong, Puneet Gupta, John Lee
ISVLSI
2003
IEEE
157views VLSI» more  ISVLSI 2003»
14 years 3 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
Shalini Ghosh, Sugato Basu, Nur A. Touba