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CASES
2001
ACM
13 years 11 months ago
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
Heidi Pan, Krste Asanovic
HIPC
2000
Springer
13 years 11 months ago
Instruction Level Distributed Processing
Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the ...
James E. Smith
TREC
2007
13 years 8 months ago
Exegy at TREC 2007 Million Query Track
Exegy’s submission for the TREC 2007 million query track consisted of results obtained by running the queries against the raw data, i.e., the data was not indexed. The hardwarea...
Naveen Singla, Ronald S. Indeck
JTRES
2010
ACM
13 years 7 months ago
The embedded Java benchmark suite JemBench
Requirements to embedded systems increase steadily. In parallel, also the performance of the processors used in these systems is improved leading to multithreaded and/or multicore...
Martin Schoeberl, Thomas B. Preußer, Sascha ...
VLSISP
2008
239views more  VLSISP 2008»
13 years 7 months ago
An Embedded Real-Time Surveillance System: Implementation and Evaluation
This paper presents the design of an embedded automated digital video surveillance system with real-time performance. Hardware accelerators for video segmentation, morphological op...
Fredrik Kristensen, Hugo Hedberg, Hongtu Jiang, Pe...