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IPPS
2007
IEEE
14 years 2 months ago
Design Alternatives for a High-Performance Self-Securing Ethernet Network Interface
This paper presents and evaluates a strategy for integrating the Snort network intrusion detection system into a high-performance programmable Ethernet network interface card (NIC...
Derek L. Schuff, Vijay S. Pai
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
14 years 1 months ago
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring
— Security is emerging as an important concern in embedded system design. The security of embedded systems is often compromised due to vulnerabilities in “trusted” software t...
Divya Arora, Srivaths Ravi, Anand Raghunathan, Nir...
LCTRTS
2005
Springer
14 years 1 months ago
Complementing software pipelining with software thread integration
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
Won So, Alexander G. Dean
ASPLOS
1998
ACM
13 years 12 months ago
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
Walter Lee, Rajeev Barua, Matthew Frank, Devabhakt...
FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
13 years 12 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus